LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;

ENTITY pwm IS
	PORT(
		clock		: IN STD_LOGIC ;
		aclr		: IN STD_LOGIC ;
		dat_in		: IN STD_LOGIC ;
		snd_in		: IN STD_LOGIC ;
		tmg_in		: IN STD_LOGIC ;
		tmg_cng		: IN STD_LOGIC ;
		tmg_out		: OUT STD_LOGIC ;
		nrzi_out		: OUT STD_LOGIC ;
		pwm_out		: OUT STD_LOGIC 
	);
END pwm;


ARCHITECTURE RTL of pwm is

--
	SIGNAL cnt_d1	: STD_LOGIC_VECTOR(3 DOWNTO 0);
	SIGNAL cnt_d2	: STD_LOGIC_VECTOR(3 DOWNTO 0);
--Low frequency(1200)
	SIGNAL cnt_l1	: STD_LOGIC_VECTOR(4 DOWNTO 0);
	SIGNAL cnt_l2	: STD_LOGIC_VECTOR(3 DOWNTO 0);
--High frequency(2200)
	SIGNAL cnt_h1	: STD_LOGIC_VECTOR(3 DOWNTO 0);
	SIGNAL cnt_h2	: STD_LOGIC_VECTOR(3 DOWNTO 0);
--Baud rate(1200)
	SIGNAL cnt_r1	: STD_LOGIC_VECTOR(4 DOWNTO 0);
	SIGNAL cnt_r2	: STD_LOGIC_VECTOR(3 DOWNTO 0);
--Ripple carry
	SIGNAL rc_d1	: STD_LOGIC;
	SIGNAL rc_d2	: STD_LOGIC;
	SIGNAL rc_l1	: STD_LOGIC;
	SIGNAL rc_l2	: STD_LOGIC;
	SIGNAL rc_h1	: STD_LOGIC;
	SIGNAL rc_h2	: STD_LOGIC;
	SIGNAL rc_r1	: STD_LOGIC;
	SIGNAL rc_r2	: STD_LOGIC;
--
	SIGNAL dec_8	: STD_LOGIC;
	SIGNAL dec_9	: STD_LOGIC;
	SIGNAL dec_A	: STD_LOGIC;
	SIGNAL dec_B	: STD_LOGIC;
	SIGNAL dec_C	: STD_LOGIC;
	SIGNAL dec_D	: STD_LOGIC;
	SIGNAL dec_E	: STD_LOGIC;

	SIGNAL reg_pw	: STD_LOGIC;
	SIGNAL nrz_sr	: STD_LOGIC_VECTOR(3 DOWNTO 0);
	SIGNAL dat_sr	: STD_LOGIC_VECTOR(3 DOWNTO 0);
	SIGNAL tmg_sr	: STD_LOGIC_VECTOR(3 DOWNTO 0);
	SIGNAL dat_n0	: STD_LOGIC;
	SIGNAL dat_n1	: STD_LOGIC;
	SIGNAL tmg_up	: STD_LOGIC;
	SIGNAL nrz_dt	: STD_LOGIC;
	SIGNAL nrzi_dt	: STD_LOGIC;
	SIGNAL brate	: STD_LOGIC;
	SIGNAL nrzi		: STD_LOGIC;
	SIGNAL sel_dt	: STD_LOGIC;

begin

	nrzi <= tmg_cng;	--kari

-- delay
	process(aclr, clock) begin
		if(aclr = '0') then
			nrz_sr <= (others => '0');
		elsif(clock'event and clock = '1') then
			nrz_sr <= nrz_sr(2 downto 0) & dat_in;
		end if;
	end process;

--	sel_dt <= nrzi_dt when (nrzi = '1') else nrz_dt;
	sel_dt <= dat_in;

	process(aclr, clock) begin
		if(aclr = '0') then
			dat_sr <= (others => '0');
		elsif(clock'event and clock = '1') then
			dat_sr <= dat_sr(2 downto 0) & sel_dt;
		end if;
	end process;

	process(aclr, clock) begin
		if(aclr = '0') then
			tmg_sr <= (others => '0');
		elsif(clock'event and clock = '1') then
			tmg_sr <= tmg_sr(2 downto 0) & tmg_in;
		end if;
	end process;

-- change
	process(aclr, clock) begin
		if(aclr = '0') then
			dat_n0 <= '0';
		elsif(clock'event and clock = '1') then
			if((dat_sr(0) = '0') and (dat_sr(1) = '1')) then
				dat_n0 <= '1';
			else
				dat_n0 <= '0';
			end if;
		end if;
	end process;

	process(aclr, clock) begin
		if(aclr = '0') then
			dat_n1 <= '0';
		elsif(clock'event and clock = '1') then
			if((dat_sr(0) = '1') and (dat_sr(1) = '0')) then
				dat_n1 <= '1';
			else
				dat_n1 <= '0';
			end if;
		end if;
	end process;

	process(aclr, clock) begin
		if(aclr = '0') then
			tmg_up <= '0';
		elsif(clock'event and clock = '1') then
			if((tmg_sr(0) = '1') and (tmg_sr(1) = '0')) then
				tmg_up <= '1';
			else
				tmg_up <= '0';
			end if;
		end if;
	end process;

-- NRZ
	process(aclr, clock) begin
		if(aclr = '0') then
			nrz_dt <= '0';
		elsif(clock'event and clock = '1') then
			if(brate = '1') then
				nrz_dt <= nrz_sr(1);
			end if;
		end if;
	end process;

-- NRZI
	process(aclr, clock) begin
		if(aclr = '0') then
			nrzi_dt <= '0';
		elsif(clock'event and clock = '1') then
			if(brate = '1') then
				if(nrz_sr(1) = '0') then
					nrzi_dt <= not nrzi_dt;
				end if;
			end if;
		end if;
	end process;

-- counter d1(1/10 or 1/11)--total 1/101 (100M/3/101 => 330k)
	process(aclr, clock) begin
		if(aclr = '0') then
			cnt_d1 <= (others => '0');
		elsif(clock'event and clock = '1') then
			if(((cnt_r2 /= "1111") and (cnt_r2 /= "0110")) and (tmg_up = '1')) then
				cnt_d1 <= "0110";
			elsif((cnt_d1 = "1111") and (rc_d2 = '1')) then
				cnt_d1 <= "0101";
			elsif(cnt_d1 = "1111") then
				cnt_d1 <= "0110";
			else
				cnt_d1 <= cnt_d1 + 1;
			end if;
		end if;
	end process;

	rc_d1 <= '1' when (cnt_d1 = "1111") else '0';

-- counter d2(1/10)
	process(aclr, clock) begin
		if(aclr = '0') then
			cnt_d2 <= (others => '0');
		elsif(clock'event and clock = '1') then
			if(((cnt_r2 /= "1111") and (cnt_r2 /= "0110")) and (tmg_up = '1')) then
					cnt_d2 <= "0110";
			elsif(rc_d1 = '1') then
				if(cnt_d2 = "1111") then
					cnt_d2 <= "0110";
				else
					cnt_d2 <= cnt_d2 + 1;
				end if;
			end if;
		end if;
	end process;

	rc_d2 <= '1' when (cnt_d2 = "1111") else '0';

-- counter r1(1/25) 100M/3/101/25/11 => 1200bps
	process(aclr, clock) begin
		if(aclr = '0') then
			cnt_r1 <= (others => '0');
		elsif(clock'event and clock = '1') then
			if((rc_d1 = '1') and (rc_d2 = '1')) then
				if(cnt_r1 = "11111") then
					cnt_r1 <= "00111";
				else
					cnt_r1 <= cnt_r1 + 1;
				end if;
			end if;
		end if;
	end process;

	rc_r1 <= '1' when (cnt_r1 = "11111") else '0';

-- counter r2(1/11)
	process(aclr, clock) begin
		if(aclr = '0') then
			cnt_r2 <= (others => '0');
		elsif(clock'event and clock = '1') then
			if((rc_d1 = '1') and (rc_d2 = '1') and (rc_r1 = '1')) then
				if(cnt_r2 = "1111") then
					cnt_r2 <= "0101";
				else
					cnt_r2 <= cnt_r2 + 1;
				end if;
			end if;
		end if;
	end process;

	rc_r2 <= '1' when (cnt_r2 = "1111") else '0';

	brate <= rc_d1 when ((cnt_r2 = "1010") and (rc_r1 = '1') and (rc_d2 = '1')) else '0';
	tmg_out <= '1' when (cnt_r2 /= "1111") else '0';

-- counter h1(1/12.5) 100M/3/101/12.5/12 => 2200Hz
-- (1/12) 100M/3/101/12/12 => 2300Hz
-- (1/13) 100M/3/101/13/12 => 2100Hz
	process(aclr, clock) begin
		if(aclr = '0') then
			cnt_h1 <= (others => '0');
		elsif(clock'event and clock = '1') then
			if((rc_d1 = '1') and (rc_d2 = '1')) then
				if(cnt_h1 = "1111") then
					if(cnt_h2(0) = '0') then
						cnt_h1 <= "0010";
					else
						cnt_h1 <= "0011";
					end if;
				else
					cnt_h1 <= cnt_h1 + 1;
				end if;
			end if;
		end if;
	end process;

	rc_h1 <= '1' when (cnt_h1 = "1111") else '0';

-- counter h2(1/12)
	process(aclr, clock) begin
		if(aclr = '0') then
			cnt_h2 <= (others => '0');
		elsif(clock'event and clock = '1') then
			if(dat_n1 = '1') then
				case(cnt_l2) is		-- 1/11
					when "0101" => cnt_h2 <= "0100";	--  0.0
					when "0110" => cnt_h2 <= "0101";	-- +0.5
					when "0111" => cnt_h2 <= "0110";	-- +0.9
					when "1000" => cnt_h2 <= "0111";	-- +1.0
					when "1001" => cnt_h2 <= "1001";	-- +0.8
					when "1010" => cnt_h2 <= "1010";	-- +0.3
					when "1011" => cnt_h2 <= "1011";	-- -0.3
					when "1100" => cnt_h2 <= "1100";	-- -0.8
					when "1101" => cnt_h2 <= "1101";	-- -1.0
					when "1110" => cnt_h2 <= "1110";	-- -0.9
					when "1111" => cnt_h2 <= "1111";	-- -0.5
					when others => cnt_h2 <= "1010";
				end case;
			elsif((rc_d1 = '1') and (rc_d2 = '1') and (rc_h1 = '1')) then
				if(cnt_h2 = "1111") then
					cnt_h2 <= "0100";
				else
					cnt_h2 <= cnt_h2 + 1;
				end if;
			end if;
		end if;
	end process;

	rc_h2 <= '1' when (cnt_h2 = "1111") else '0';

-- counter l1(1/25) 100M/3/101/25/11 => 1200Hz
	process(aclr, clock) begin
		if(aclr = '0') then
			cnt_l1 <= (others => '0');
		elsif(clock'event and clock = '1') then
			if((rc_d1 = '1') and (rc_d2 = '1')) then
				if(cnt_l1 = "11111") then
					cnt_l1 <= "00111";
				else
					cnt_l1 <= cnt_l1 + 1;
				end if;
			end if;
		end if;
	end process;

	rc_l1 <= '1' when (cnt_l1 = "11111") else '0';

-- counter l2(1/11)
	process(aclr, clock) begin
		if(aclr = '0') then
			cnt_l2 <= (others => '0');
		elsif(clock'event and clock = '1') then
			if(dat_n0 = '1') then
				case(cnt_h2) is		-- 1/12
					when "0100" => cnt_l2 <= "0101";	--  0.0
					when "0101" => cnt_l2 <= "0110";	-- +0.5
					when "0110" => cnt_l2 <= "0111";	-- +0.9
					when "0111" => cnt_l2 <= "1000";	-- +1.0
					when "1000" => cnt_l2 <= "1001";	-- +0.9
					when "1001" => cnt_l2 <= "1010";	-- +0.5
					when "1010" => cnt_l2 <= "1011";	--  0.0
					when "1011" => cnt_l2 <= "1100";	-- -0.5
					when "1100" => cnt_l2 <= "1101";	-- -0.9
					when "1101" => cnt_l2 <= "1101";	-- -1.0
					when "1110" => cnt_l2 <= "1110";	-- -0.9
					when "1111" => cnt_l2 <= "1111";	-- -0.5
					when others => cnt_l2 <= "1010";
				end case;
			elsif((rc_d1 = '1') and (rc_d2 = '1') and (rc_l1 = '1')) then
				if(cnt_l2 = "1111") then
					cnt_l2 <= "0101";
				else
					cnt_l2 <= cnt_l2 + 1;
				end if;
			end if;
		end if;
	end process;

	rc_l2 <= '1' when (cnt_l2 = "1111") else '0';

--
	dec_8 <= '1' when (cnt_d2 >= "1000") else '0';	-- -1.0 - -0.8
	dec_9 <= '1' when (cnt_d2 >= "1001") else '0';	-- -0.7 - -0.5 
	dec_A <= '1' when (cnt_d2 >= "1010") else '0';	-- -0.4 - -0.2
	dec_B <= '1' when (cnt_d2 >= "1011") else '0';	-- -0.1 - +0.1
	dec_C <= '1' when (cnt_d2 >= "1100") else '0';	-- +0.2 - +0.4
	dec_D <= '1' when (cnt_d2 >= "1101") else '0';	-- +0.5 - +0.7
	dec_E <= '1' when (cnt_d2 >= "1110") else '0';	-- +0.8 - +1.0

-- 
	process(aclr, clock) begin
		if(aclr = '0') then
			reg_pw <= '0';
		elsif(clock'event and clock = '1') then
			if((rc_d1 = '1') and (rc_d2 = '1')) then
				reg_pw <= '0';
			elsif(snd_in = '0') then
				reg_pw <= dec_B;					-- zero
			elsif(dat_sr(3) = '1') then
				case(cnt_h2) is		-- 1/12
					when "0100" => reg_pw <= dec_B;	--  0.0
					when "0101" => reg_pw <= dec_D;	-- +0.5
					when "0110" => reg_pw <= dec_E;	-- +0.9
					when "0111" => reg_pw <= dec_E;	-- +1.0
					when "1000" => reg_pw <= dec_E;	-- +0.9
					when "1001" => reg_pw <= dec_D;	-- +0.5
					when "1010" => reg_pw <= dec_B;	--  0.0
					when "1011" => reg_pw <= dec_9;	-- -0.5
					when "1100" => reg_pw <= dec_8;	-- -0.9
					when "1101" => reg_pw <= dec_8;	-- -1.0
					when "1110" => reg_pw <= dec_8;	-- -0.9
					when "1111" => reg_pw <= dec_9;	-- -0.5
					when others => reg_pw <= '0';
				end case;
			else
				case(cnt_l2) is		-- 1/11
					when "0101" => reg_pw <= dec_B;	--  0.0
					when "0110" => reg_pw <= dec_D;	-- +0.5
					when "0111" => reg_pw <= dec_E; -- +0.9
					when "1000" => reg_pw <= dec_E; -- +1.0
					when "1001" => reg_pw <= dec_E; -- +0.8
					when "1010" => reg_pw <= dec_C; -- +0.3
					when "1011" => reg_pw <= dec_A; -- -0.3
					when "1100" => reg_pw <= dec_8;	-- -0.8
					when "1101" => reg_pw <= dec_8;	-- -1.0
					when "1110" => reg_pw <= dec_8;	-- -0.9
					when "1111" => reg_pw <= dec_9;	-- -0.5
					when others => reg_pw <= '0';
				end case;
			end if;
		end if;
	end process;

-- PWM
	pwm_out <= reg_pw;

end RTL;