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-- DW2005 FM reciver for Spartan-2 Top module
-- Ver 00
-- 19 Dec. 2004
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY UNISIM;
USE UNISIM.Vcomponents.ALL;

ENTITY TOP is
port (
	SYSCLK 	: in std_logic;						--32MHz
	xRESET 	: in std_logic;						--SW1
	FMIN 	: in std_logic_vector(7 downto 0);	--for A/D
	CLKOUT 	: out std_logic;					--16MHz
	LED_S4 	: out std_logic;					--LED5-12
	LED5 	: out std_logic;
	LED6 	: out std_logic;
	LED7 	: out std_logic;
	LED8 	: out std_logic;
	LED9 	: out std_logic;
	LED10 	: out std_logic;
	LED11 	: out std_logic;
	LED12 	: out std_logic;
	PWMOUT 	: out std_logic;					--cut off 4kHz
	DMOUT 	: out std_logic_vector(11 downto 0)	--for D/A
	);
END TOP;

ARCHITECTURE RTL of TOP is

COMPONENT RECV 
port (
	CLK 	: in std_logic;
	RESET 	: in std_logic;
	FMIN 	: in std_logic_vector(7 downto 0);
		--FMIN(8,0,t)
		-- S.XXXXXXX
		-- -1 to 1-(1/2**7)
	DMOUT 	: out std_logic_vector(11 downto 0)
		--DMOUT(12,4,t)
		-- SXXXX.XXXXXXX
		-- -16 to 16-(1/2**7)
	);
END COMPONENT;

COMPONENT PWM 
port (
	CLK 	: in std_logic;
	RESET 	: in std_logic;
	DATIN 	: in std_logic_vector(11 downto 0);
	PWMOUT 	: out STD_LOGIC 
	);
END COMPONENT;

------------------------------------------------------------------------------------
--
-- Signals 
--
signal iCLK 	: std_logic;
signal CLK 		: std_logic;
signal RESET 	: std_logic;

signal iFMIN 	: std_logic_vector(7 downto 0);
signal iDMOUT 	: std_logic_vector(11 downto 0);

------------------------------------------------------------------------------------------------------------------------------------------------------------------------
--
-- Start of circuit description
--
BEGIN

	RESET 	<= not xRESET;

--center meter
	LED_S4 	<= '0';

	LED12 	<= not iDMOUT(11) and     iDMOUT(10) and     iDMOUT(9);
	LED11 	<= not iDMOUT(11) and     iDMOUT(10) and not iDMOUT(9);
	LED10 	<= not iDMOUT(11) and not iDMOUT(10) and     iDMOUT(9);
	LED9 	<= not iDMOUT(11) and not iDMOUT(10) and not iDMOUT(9);
	LED8 	<=     iDMOUT(11) and     iDMOUT(10) and     iDMOUT(9);
	LED7 	<=     iDMOUT(11) and     iDMOUT(10) and not iDMOUT(9);
	LED6 	<=     iDMOUT(11) and not iDMOUT(10) and     iDMOUT(9);
	LED5 	<=     iDMOUT(11) and not iDMOUT(10) and not iDMOUT(9);

--clock generator
	process(RESET, SYSCLK)	
	begin
		if(RESET = '1') then
			iCLK <= '0';
		elsif (SYSCLK'event and SYSCLK='1') then
			iCLK <= not iCLK;
		end if;
	end process;

U1 : BUFG
	port map(
		I => iCLK,
		O => CLK
	);

--A/D converter
	process(RESET, CLK)	
	begin
		if(RESET = '1') then
			iFMIN <= (others => '0');
		elsif (CLK'event and CLK='0') then
			iFMIN <= (not FMIN(7)) & FMIN(6 downto 0);
		end if;
	end process;

	CLKOUT <= iCLK;

--FM receiver
U2 : RECV
	port map(
		CLK 	=> CLK,
		RESET 	=> RESET,
		FMIN 	=> iFMIN,
		DMOUT 	=> iDMOUT
	);

	DMOUT <= iDMOUT;

--D/A converter
U3 : PWM
	port map(
		CLK 	=> CLK,
		RESET 	=> RESET,
		DATIN 	=> iDMOUT,
		PWMOUT 	=> PWMOUT
	);

END RTL ;