library STD,IEEE;

use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_textio.all;
use std.textio.all;

entity test2 is
end test2;
 	
architecture SIM of test2 is

component RECV
	port(
	CLK : in std_logic;
	RESET : in std_logic;
	FMIN : in std_logic_vector(7 downto 0 );
	DMOUT : out std_logic_vector(11 downto 0 )
	);
end component;

constant CLK_CYCLE : TIME := 30 ns;--1/16M=62.5ns

signal	RESET : std_logic;
signal	CLK : std_logic;

signal	FMIN : std_logic_vector(7 downto 0);
signal	DMOUT : std_logic_vector(11 downto 0);

signal	A_FMIN : std_logic_vector(7 downto 0);
signal	A_DMOUT : std_logic_vector(11 downto 0);

begin

U0 : RECV
port map(
	CLK => CLK,
	RESET => RESET,
	FMIN => FMIN,
	DMOUT => DMOUT
	);

A_FMIN <= (not FMIN(7)) & FMIN(6 downto 0);
A_DMOUT <= (not DMOUT(11)) & DMOUT(10 downto 0);

--Reset
process begin
		RESET <= '1';
	wait for CLK_CYCLE*6.5;
		RESET <= '0';
	wait;
end process;

--Clock
process begin
		CLK <= '0';
	wait for CLK_CYCLE*10;

	loop
			CLK<='1';
		wait for CLK_CYCLE;
			CLK<='0';
		wait for CLK_CYCLE;
	end loop;

	wait;
end process;

--Data
process

	file R_FILE : text open read_mode  is "455k.txt";
	file W_file	: text open write_mode is "result.txt";
	variable R_LINE: line; --read print buffer;
	variable W_LINE: line; --write print buffer;
	variable R_DATA: std_logic_vector(7 downto 0);
	variable W_DATA: std_logic_vector(11 downto 0);

begin

while ( not endfile(R_FILE) ) loop
	readline(R_FILE,R_LINE);
	read(R_LINE,R_DATA);
	FMIN <= R_DATA;

	wait for CLK_CYCLE;
	  
	W_DATA := DMOUT;
	write(W_LINE,W_DATA);
	writeline(W_FILE,W_LINE); 

	wait for CLK_CYCLE;
	      
end loop;

wait;

end process;

end SIM;

configuration CFG_TEST of test2 is
	for SIM
	end for;
end CFG_TEST;