--------------------------------------------------------------------------------
-- DW2005 FM reciver for Spartan-2 Memory module
-- Ver 00 memory
-- 19 Dec. 2004
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY UNISIM;
USE UNISIM.Vcomponents.ALL;

ENTITY RAMB is
port (
	CLK 	: in std_logic;
	DIN 	: in std_logic_vector(7 downto 0);
	DOUT 	: out std_logic_vector(7 downto 0);
	WE 		: in std_logic;
	WADR 	: in std_logic_vector(9 downto 0);
	RADR 	: in std_logic_vector(9 downto 0)
	);
end RAMB;

ARCHITECTURE RTL of RAMB is

COMPONENT RAMB4_S4_S4
port (
	DOA 	: out STD_LOGIC_VECTOR (3 downto 0);
	DOB 	: out STD_LOGIC_VECTOR (3 downto 0);
	ADDRA 	: in STD_LOGIC_VECTOR (9 downto 0);
	ADDRB 	: in STD_LOGIC_VECTOR (9 downto 0);
	CLKA 	: in STD_ULOGIC;
	CLKB 	: in STD_ULOGIC;
	DIA 	: in STD_LOGIC_VECTOR (3 downto 0);
	DIB 	: in STD_LOGIC_VECTOR (3 downto 0);
	ENA 	: in STD_ULOGIC;
	ENB 	: in STD_ULOGIC;
	RSTA 	: in STD_ULOGIC;
	RSTB 	: in STD_ULOGIC;
	WEA 	: in STD_ULOGIC;
	WEB 	: in STD_ULOGIC
	);
END COMPONENT;

------------------------------------------------------------------------------------
--
-- Signals 
--
signal DIH 	: std_logic_vector(3 downto 0 );
signal DIL 	: std_logic_vector(3 downto 0 );
signal DOH 	: std_logic_vector(3 downto 0 );
signal DOL 	: std_logic_vector(3 downto 0 );

------------------------------------------------------------------------------------------------------------------------------------------------------------------------
--
-- Start of circuit description
--
BEGIN

	DIH 	<= DIN(7 downto 4);
	DIL 	<= DIN(3 downto 0);
	DOUT 	<= DOH & DOL;

U211 : RAMB4_S4_S4
	port map (
		DOA 	=> open,
		DOB 	=> DOH,
		ADDRA 	=> WADR,
		ADDRB 	=> RADR,
		CLKA 	=> CLK,
		CLKB 	=> CLK,
		DIA 	=> DIH,
		DIB 	=> "0000",
		ENA 	=> '1',
		ENB 	=> '1',
		RSTA 	=> '0',
		RSTB 	=> '0',
		WEA 	=> WE,
		WEB 	=> '0'
	);

U212 : RAMB4_S4_S4
	port map (
		DOA 	=> open,
		DOB 	=> DOL,
		ADDRA 	=> WADR,
		ADDRB 	=> RADR,
		CLKA 	=> CLK,
		CLKB 	=> CLK,
		DIA 	=> DIL,
		DIB 	=> "0000",
		ENA 	=> '1',
		ENB 	=> '1',
		RSTA 	=> '0',
		RSTB 	=> '0',
		WEA 	=> WE,
		WEB 	=> '0'
	);

END RTL ;