LIBRARY IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY PWM IS
	PORT(
		CLK		: IN STD_LOGIC ;
		RESET		: IN STD_LOGIC ;
		DATIN		: IN std_logic_vector(11 downto 0);
		PWMOUT		: OUT STD_LOGIC 
	);
END PWM;


ARCHITECTURE RTL of PWM is

--
	SIGNAL cnt_d1	: STD_LOGIC_VECTOR(2 DOWNTO 0);
	SIGNAL cnt_d2	: STD_LOGIC_VECTOR(2 DOWNTO 0);
	SIGNAL rc_d1	: STD_LOGIC;
	SIGNAL rc_d2	: STD_LOGIC;
	SIGNAL width	: STD_LOGIC_VECTOR(5 DOWNTO 0);
	SIGNAL pulse		: STD_LOGIC;

begin

--
	process(RESET, CLK) begin
		if(RESET = '1') then
				width <= (others => '0');
		elsif(CLK'event and CLK = '1') then
			if((rc_d1 = '1') and (rc_d2 = '1'))then
				width <= (not DATIN(11)) & DATIN(10 downto 6);
			end if;
		end if;
	end process;

-- counter (16M/16 => 1M)
	process(RESET, CLK) begin
		if(RESET = '1') then
			cnt_d1 <= (others => '0');
		elsif(CLK'event and CLK = '1') then
			cnt_d1 <= cnt_d1 + 1;
		end if;
	end process;

	rc_d1 <= '1' when (cnt_d1 = "111") else '0';

-- counter (250k/8 => 64k)
	process(RESET, CLK) begin
		if(RESET = '1') then
			cnt_d2 <= (others => '0');
		elsif(CLK'event and CLK = '1') then
			if(rc_d1 = '1') then
				cnt_d2 <= cnt_d2 + 1;
			end if;
		end if;
	end process;

	rc_d2 <= '1' when (cnt_d2 = "111") else '0';

--
	process(RESET, CLK) begin
		if(RESET = '1') then
				pulse <= '0';
		elsif(CLK'event and CLK = '1') then
			if((rc_d1 = '1') and (rc_d2 = '1'))then
				pulse <= '1';
			elsif(width = (cnt_d2 & cnt_d1)) then
				pulse <= '0';
			end if;
		end if;
	end process;

-- PWM
	PWMOUT <= pulse;

end RTL;